624 search results - page 3 / 125 » Test set compaction algorithms for combinational circuits |
CEC
2005
IEEE
14 years 19 days ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
TC
1998
13 years 6 months ago
1998
—Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The ...
ATS
1998
IEEE
13 years 11 months ago
1998
IEEE
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
EURODAC
1995
IEEE
13 years 10 months ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...