13 search results - page 1 / 3 » Testable Path Delay Fault Cover for Sequential Circuits |
JISE
2000
13 years 7 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
VLSID
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...