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» Testing Digital Circuits with Constraints
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ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
GECCO
2006
Springer
215views Optimization» more  GECCO 2006»
14 years 8 days ago
A multi-chromosome approach to standard and embedded cartesian genetic programming
Embedded Cartesian Genetic Programming (ECGP) is an extension of Cartesian Genetic Programming (CGP) that can automatically acquire, evolve and re-use partial solutions in the for...
James Alfred Walker, Julian Francis Miller, Rachel...
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
14 years 27 days ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
14 years 2 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan
ROBIO
2006
IEEE
103views Robotics» more  ROBIO 2006»
14 years 2 months ago
Processing of an Embedded Tactile Matrix Sensor
— A fully embedded tactile/force sensor system to be installed on the phalanges of a robot hand is presented in this paper. The sensor consists of a distributed array of analog t...
Giorgio Cannata, Marco Maggiali