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» Testing Digital Circuits with Constraints
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ASPDAC
2010
ACM
637views Hardware» more  ASPDAC 2010»
13 years 6 months ago
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 3 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
MM
2009
ACM
203views Multimedia» more  MM 2009»
14 years 1 months ago
Distance metric learning from uncertain side information with application to automated photo tagging
Automated photo tagging is essential to make massive unlabeled photos searchable by text search engines. Conventional image annotation approaches, though working reasonably well o...
Lei Wu, Steven C. H. Hoi, Rong Jin, Jianke Zhu, Ne...
IPSN
2010
Springer
13 years 10 months ago
Hibernets: energy-efficient sensor networks using analog signal processing
In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy ...
Brandon Rumberg, David W. Graham, Vinod Kulathuman...
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
14 years 3 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...