As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Automated photo tagging is essential to make massive unlabeled photos searchable by text search engines. Conventional image annotation approaches, though working reasonably well o...
Lei Wu, Steven C. H. Hoi, Rong Jin, Jianke Zhu, Ne...
In-network processing is recommended for many sensor network applications to reduce communication and improve energy efficiency. However, constraints on memory, speed, and energy ...
Brandon Rumberg, David W. Graham, Vinod Kulathuman...
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...