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» Testing Patterns

28

ATS
2000
IEEE

86views Hardware» more ATS 2000»

An adjacency-based test pattern generator for low power BIST design

14 years 2 months ago

An adjacency-based test pattern generator for low power BIST design

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Patrick Girard, Loïs Guiller, Christian Landr...

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21

ITC
2000
IEEE

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Using on-chip test pattern compression for full scan SoC designs

14 years 2 months ago

Using on-chip test pattern compression for full scan SoC designs

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Helmut Lang, Jens Pfeiffer, Jeff Maguire

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20

VLSID
1999
IEEE

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POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing

14 years 2 months ago

POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing

Download www.ra.informatik.uni-stuttgart.de

Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik

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25

ATS
1998
IEEE

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A Test Pattern Generation Algorithm Exploiting Behavioral Information

14 years 2 months ago

A Test Pattern Generation Algorithm Exploiting Behavioral Information

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This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...

Silvia Chiusano, Fulvio Corno, Paolo Prinetto

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21

GLVLSI
1997
IEEE

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An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation

14 years 2 months ago

An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation

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H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor V...

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