1610 search results - page 30 / 322 » Testing Patterns |
ICST
2011
IEEE
13 years 1 months ago
2011
IEEE
—Generated test cases are good at systematically exploring paths and conditions in software. However, generated test cases often do not make sense. We adapt test case generation ...
VTS
1995
IEEE
14 years 1 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
ECRTS
2008
IEEE
13 years 11 months ago
2008
IEEE
The schedulability testing for the deferrable scheduling algorithm for fixed priority transactions (DS-FP) remains
ET
2002
13 years 9 months ago
2002
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...