1610 search results - page 31 / 322 » Testing Patterns |
VTS
2005
IEEE
14 years 3 months ago
2005
IEEE
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
FDTC
2010
Springer
13 years 8 months ago
2010
Springer
The testability of the cryptographic cores brings in an extra dimension to the process of digital circuits testing
ASPDAC
1998
ACM
14 years 2 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
DDECS
2007
IEEE
14 years 4 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
ATS
2009
IEEE
14 years 4 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...