1610 search results - page 37 / 322 » Testing Patterns |
ITC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
ICST
2010
IEEE
13 years 8 months ago
2010
IEEE
Mobile computing systems provide new challenges for verification. One of them is the dynamicity of the system structure, with mobility-induced connections and disconnections, dynam...
DFT
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
DFT
1997
IEEE
14 years 2 months ago
1997
IEEE
The paper presents a test pattern generation and fault simulation methodology for the detection of catastrophic faults in analogue circuits. The test methodology chosen for evalua...
ITC
1998
IEEE
14 years 2 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...