Sciweavers

1610 search results - page 46 / 322
» Testing Patterns
Sort
View
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
14 years 2 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
PAMI
2008
159views more  PAMI 2008»
13 years 10 months ago
Analysis of Head Gesture and Prosody Patterns for Prosody-Driven Head-Gesture Animation
We propose a new two-stage framework for joint analysis of head gesture and speech prosody patterns of a speaker toward automatic realistic synthesis of head gestures from speech p...
Mehmet Emre Sargin, Yücel Yemez, Engin Erzin,...
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
14 years 3 months ago
Test Vector Generation Based on Correlation Model for Ratio-Iddq
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
ACMSE
2010
ACM
13 years 8 months ago
An ontology-driven rote extractor for pattern disambiguation
In this paper, we describe an ontology-driven pattern disambiguation process for Rote Extractors. Our approach can generate lexical patterns for a particular relation from unrestr...
Sheng Yin, Ismailcem Budak Arpinar
EVOW
2001
Springer
14 years 2 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...