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ATS
2009
IEEE
132views Hardware» more  ATS 2009»
14 years 4 months ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
14 years 2 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
14 years 2 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
14 years 2 months ago
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and par...
Amir Attarha, Mehrdad Nourani
DATE
2003
IEEE
108views Hardware» more  DATE 2003»
14 years 3 months ago
EBIST: A Novel Test Generator with Built-In Fault Detection Capability
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...
Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakr...