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ETS
2006
IEEE
100views Hardware» more  ETS 2006»
14 years 1 months ago
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
— Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships ...
Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun,...
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
14 years 24 days ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
13 years 10 months ago
Defect aware X-filling for low-power scan testing
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
S. Balatsouka, V. Tenentes, Xrysovalantis Kavousia...
ET
2000
145views more  ET 2000»
13 years 7 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
APSEC
2010
IEEE
13 years 2 months ago
Testing Inter-layer and Inter-task Interactions in RTES Applications
Abstract--Real-time embedded systems (RTESs) are becoming increasingly ubiquitous, controlling a wide variety of popular and safety-critical devices. Effective testing techniques c...
Ahyoung Sung, Witawas Srisa-an, Gregg Rothermel, T...