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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
Irith Pomeranz, Sudhakar M. Reddy
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
14 years 1 months ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
14 years 27 days ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
DATE
2010
IEEE
149views Hardware» more  DATE 2010»
14 years 8 days ago
Efficient decision ordering techniques for SAT-based test generation
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
Mingsong Chen, Xiaoke Qin, Prabhat Mishra
COMPSAC
2007
IEEE
13 years 12 months ago
Piping Classification to Metamorphic Testing: An Empirical Study towards Better Effectiveness for the Identification of Failures
Mesh simplification is a mainstream technique to render graphics responsively in modern graphical software. However, the graphical nature of the output poses a test oracle problem...
W. K. Chan, Jeffrey C. F. Ho, T. H. Tse