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ICCAD
1994
IEEE
83views Hardware» more  ICCAD 1994»
13 years 11 months ago
A new built-in self-test approach for digital-to-analog and analog-to-digital converters
This paper proposes a test approach and circuitry suitable for built-in self-test (BIST) of digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, linearity...
Karim Arabi, Bozena Kaminska, Janusz Rzeszut
WCE
2007
13 years 8 months ago
An Approach to Test Aspect-oriented Programs
— Software testing is a perennial problem, consequently it scores scant attention. An inclusion to testing challenges is aspect-oriented paradigm, which has a dichotomy of core a...
M. N. Qamar, Aziz Nadeem, R. Aziz
DATE
2006
IEEE
134views Hardware» more  DATE 2006»
14 years 1 months ago
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
1 This paper presents a test scheduling approach for system-onchip production tests with peak-power constraints. An abort-onfirst-fail test approach is assumed, whereby the test is...
Zhiyuan He, Zebo Peng, Petru Eles
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 1 months ago
Concurrent core test for SOC using shared test set and scan chain disable
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
Gang Zeng, Hideo Ito
GECCO
2006
Springer
253views Optimization» more  GECCO 2006»
13 years 11 months ago
A novel approach to optimize clone refactoring activity
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...
Salah Bouktif, Giuliano Antoniol, Ettore Merlo, Ma...