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DFT
2003
IEEE
114views VLSI» more  DFT 2003»
14 years 1 months ago
CodSim -- A Combined Delay Fault Simulator
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, We...
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 1 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
DATE
2000
IEEE
128views Hardware» more  DATE 2000»
14 years 26 days ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
Kei Hirose, Hiroto Yasuura
DAC
2000
ACM
14 years 24 days ago
Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
This paper develops the noise-counterparts to familiar delay formulas like Elmore or PRIMO. By matching the first few moments of the network’s transfer impedance, we obtain effi...
Bernard N. Sheehan
DAC
1999
ACM
14 years 23 days ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton