The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
Abstract. We consider the iterates of bilinear functions over the semiring (max, +). Equivalently, our object of study can be viewed as recognizable tree series over the semiring (...
Sabrina Mantaci, Vincent D. Blondel, Jean Mairesse
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...