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CODES
1998
IEEE
14 years 2 months ago
Software timing analysis using HW/SW cosimulation and instruction set simulator
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-V...
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
FPGA
1995
ACM
149views FPGA» more  FPGA 1995»
14 years 1 months ago
PathFinder: A Negotiation-based Performance-driven Router for FPGAs
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
Larry McMurchie, Carl Ebeling
UIST
1991
ACM
14 years 1 months ago
On temporal-spatial realism in the virtual reality environment
The Polhemus Isotrak is often used as an orientation and position tracking device in virtual reality environments. When it is used to dynamically determine the user's viewpoi...
Jiandong Liang, Christopher D. Shaw, Mark Green
APCCAS
2006
IEEE
252views Hardware» more  APCCAS 2006»
14 years 2 days ago
A Display Order Oriented Scalable Video Decoder
As network technologies advance, Scalable Video Coding (SVC) has become increasingly popular due to its universal multimedia access capability and competitive compression performan...
Jia-Bin Huang, Yu-Kun Lin, Tian-Sheuan Chang