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» The Design and Implementation of the A2QM3 System
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HPCA
2006
IEEE
14 years 10 months ago
Completely verifying memory consistency of test program executions
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
Chaiyasit Manovit, Sudheendra Hangal
SIGMOD
2008
ACM
182views Database» more  SIGMOD 2008»
14 years 10 months ago
Multi-tenant databases for software as a service: schema-mapping techniques
In the implementation of hosted business services, multiple tenants are often consolidated into the same database to reduce total cost of ownership. Common practice is to map mult...
Stefan Aulbach, Torsten Grust, Dean Jacobs, Alfons...
DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 5 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 4 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
HIPEAC
2007
Springer
14 years 4 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
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