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» The Design and Performance of a Conflict-Avoiding Cache
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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 3 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
14 years 1 months ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
TPDS
2010
155views more  TPDS 2010»
13 years 6 months ago
Cooperative Caching in Wireless P2P Networks: Design, Implementation, and Evaluation
—Some recent studies have shown that cooperative cache can improve the system performance in wireless P2P networks such as ad hoc networks and mesh networks. However, all these s...
Jing Zhao, Ping Zhang, Guohong Cao, Chita R. Das
HPCA
2001
IEEE
14 years 8 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
TVLSI
2010
13 years 3 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...