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» The Design and Performance of a Conflict-Avoiding Cache
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IJHPCA
2006
122views more  IJHPCA 2006»
13 years 8 months ago
A New Hardware Monitor Design to Measure Data Structure-Specific Cache Eviction Information
In this paper, we propose a hardware performance monitor that provides support not only for measuring cache misses and the addresses associated with them, but also for determining...
Bryan R. Buck, Jeffrey K. Hollingsworth
CF
2005
ACM
13 years 10 months ago
Skewed caches from a low-power perspective
The common approach to reduce cache conflicts is to increase the associativity. From a dynamic power perspective this associativity comes at a high cost. In this paper we present...
Mathias Spjuth, Martin Karlsson, Erik Hagersten
FPL
2007
Springer
78views Hardware» more  FPL 2007»
14 years 2 months ago
Dynamic Cache Switching in Reconfigurable Embedded Systems
The idea of changing cache attributes to suit an application has been explored for single programs. As the popularity of reconfigurable softcore systems grows and these systems in...
John Shield, Peter Sutton, Philip Machanick
ISCA
2011
IEEE
273views Hardware» more  ISCA 2011»
13 years 4 days ago
Bypass and insertion algorithms for exclusive last-level caches
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramone...
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 5 months ago
Exploring the interplay of yield, area, and performance in processor caches
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers