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» The Entropy of FPGA Reconfiguration
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FCCM
2005
IEEE
151views VLSI» more  FCCM 2005»
14 years 4 months ago
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems
In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
DAC
1999
ACM
14 years 3 months ago
Dynamically Reconfigurable Architecture for Image Processor Applications
This work presents an overview of the principles that underlie the speed-up achievable by dynamic hardware reconfiguration, proposes a more precise taxonomy for the execution mode...
Alexandro M. S. Adário, Eduardo L. Roehe, S...
TIM
2010
188views Education» more  TIM 2010»
13 years 5 months ago
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
Kyprianos Papadimitriou, Antonis Anyfantis, Aposto...
FCCM
2009
IEEE
106views VLSI» more  FCCM 2009»
14 years 2 months ago
Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, we present a polynomial time al...
Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
DAC
2008
ACM
14 years 12 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...