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» The Expressive Power of Synchronizations
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ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
15 years 10 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
15 years 8 months ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...
IPPS
2006
IEEE
15 years 10 months ago
A calculus of functional BSP programs with projection
Bulk Synchronous Parallel ML (BSML) is an extension of the functional language Objective Caml to program Bulk Synchronous Parallel (BSP) algorithms. It is deterministic, deadlock ...
Frédéric Loulergue
ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
15 years 9 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
134
Voted
CSCW
1998
ACM
15 years 8 months ago
Design for Individuals, Design for Groups: Tradeoffs between Power and Workspace Awareness
Users of synchronous groupware systems act both as individuals and as members of a group, and designers must try to support both roles. However, the requirements of individuals an...
Carl Gutwin, Saul Greenberg