The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Bulk Synchronous Parallel ML (BSML) is an extension of the functional language Objective Caml to program Bulk Synchronous Parallel (BSP) algorithms. It is deterministic, deadlock ...
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
Users of synchronous groupware systems act both as individuals and as members of a group, and designers must try to support both roles. However, the requirements of individuals an...