Sciweavers

2424 search results - page 118 / 485
» The High Level Architecture for Simulations
Sort
View
ISCAS
1993
IEEE
133views Hardware» more  ISCAS 1993»
14 years 1 months ago
An efficient FIR filter architecture
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
Joseph B. Evans
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
14 years 14 days ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
14 years 1 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
RAS
2007
150views more  RAS 2007»
13 years 8 months ago
Evolution of fuzzy behaviors for multi-robotic system
In a multi-robotic system, robots interact with each other in a dynamically changing environment. The robots need to be intelligent both at the individual and group levels. In thi...
Prahlad Vadakkepat, Xiao Peng, Boon Kiat Quek, Ton...
DAC
2006
ACM
14 years 10 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr