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» The High Level Architecture for Simulations
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ICDCSW
2002
IEEE
15 years 11 months ago
DBGlobe: A Data-Centric Approach to Global Computing
In the near future, there will be increasingly powerful computers in smart cards, telephones, and other information appliances. This will create a massive infrastructure composed ...
Alexandros Karakasidis, Evaggelia Pitoura
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
15 years 5 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
ISPASS
2009
IEEE
16 years 27 days ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
196
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SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
15 years 11 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
IWSSD
2000
IEEE
15 years 10 months ago
Issues in Analyzing the Behavior of Event Dispatching Systems
A good architecture is a necessary condition to guarantee that the expected levels of performance, availability, fault tolerance, and scalability are achieved by the implemented s...
Giovanni Bricconi, Emma Tracanella, Elisabetta Di ...