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DATE
1998
IEEE
116views Hardware» more  DATE 1998»
15 years 10 months ago
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
Isidoro Urriza, José I. Artigas, José...
ITNG
2007
IEEE
16 years 9 days ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
NOSSDAV
2009
Springer
16 years 19 days ago
A delaunay triangulation architecture supporting churn and user mobility in MMVEs
This article proposes a new distributed architecture for update message exchange in massively multi-user virtual environments (MMVE). MMVE applications require delivery of updates...
Mohsen Ghaffari, Behnoosh Hariri, Shervin Shirmoha...
DFMA
2005
IEEE
122views Multimedia» more  DFMA 2005»
15 years 11 months ago
Distributed Management Architecture for Multimedia Conferencing Using SIP
As various multimedia communication services are increasingly required by Internet users, several signaling protocols have been proposed for the efficient control of multimedia co...
Yeong-Hun Cho, Moon-Sang Jeong, Jong-Tae Park, Wee...
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 10 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald