2424 search results - page 208 / 485 » The High Level Architecture for Simulations |
137
click to vote
ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
165
click to vote
ICCAD
2009
IEEE
15 years 3 months ago
2009
IEEE
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
184
click to vote
ATAL
2005
Springer
15 years 11 months ago
2005
Springer
There has been much research investigating team cognition, naturalistic decision making, and collaborative technology as it relates to real world, complex domains of practice. How...
180
click to vote
MICRO
2003
IEEE
15 years 11 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
170
click to vote
INFFUS
2007
15 years 6 months ago
2007
The Swedish Defence Research Agency (FOI) has developed a concept demonstrator called the Information Fusion Demonstrator 2003 (IFD03) for demonstrating information fusion methodo...