2424 search results - page 41 / 485 » The High Level Architecture for Simulations |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
WSC
1997
13 years 10 months ago
1997
The DoD High Level architecture (HLA) has recently become the required method for the interconnection of all DoD computer simulations. The HLA addresses the rules by which simulat...
VLSID
2000
IEEE
14 years 1 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
SAMOS
2005
Springer
14 years 2 months ago
2005
Springer
Design space exploration plays an essential role in the system-level design of embedded systems. It is imperative therefore to have efficient and effective exploration tools in th...