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NETWORKING
2004
13 years 10 months ago
Comparative Evaluation of Two Scalable QoS Architectures
This paper performs a comparative evaluation of two QoS architectures, RSVP Reservation Aggregation and Scalable ReservationBased QoS, aimed at providing QoS levels similar to the ...
Rui Prior, Susana Sargento, Pedro Brandão, ...
TPDS
2008
113views more  TPDS 2008»
13 years 8 months ago
Evaluating a High-Level Parallel Language (GpH) for Computational GRIDs
Computational Grids potentially offer low cost, readily available, and large-scale high-performance platforms. For the parallel execution of programs, however, computational GRIDs ...
Abdallah Al Zain, Philip W. Trinder, Greg Michaels...
HPCA
1998
IEEE
14 years 9 days ago
Non-Stalling CounterFlow Architecture
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
14 years 5 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 10 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson