Sciweavers

2424 search results - page 47 / 485
» The High Level Architecture for Simulations
Sort
View
SBACPAD
2008
IEEE
206views Hardware» more  SBACPAD 2008»
14 years 3 months ago
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
Thiago S. M. C. de Farias, Mozart W. S. Almeida, J...
SIMULATION
2002
118views more  SIMULATION 2002»
13 years 8 months ago
Simulation of Tactical Communications Systems by Inferring Detailed Data from the Joint Theater-Level Computer-Aided Exercises
- In this paper, a new scheme for the simulation of tactical communications systems is introduced where the mobility, call and availability patterns for the communications equipmen...
Erdal Cayirci, Cem Ersoy
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
14 years 1 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
CASES
2007
ACM
14 years 21 days ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall