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    WSC
    2000
    135views Modeling And Simulation» more  WSC 2000»
    Abstract modeling for engineering and engagement level simulations
    13 years 10 months ago
    Abstract modeling for engineering and engagement level simulations
    Download  www.informs-sim.org
    MODELING FOR ENGINEERING AND ENGAGEMENT LEVEL SIMULATIONS Robert M. McGraw Richard A. MacDonald RAM Laboratories, Inc. 6540 Lusk Boulevard, Suite C200 San Diego, CA 92121, U.S.A. ...
    Robert M. McGraw, Richard A. MacDonald
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    DATE
    2005
    IEEE
    164views Hardware» more  DATE 2005»
    Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
    13 years 10 months ago
    Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture
    Download  dtl.yonsei.ac.kr
    Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-lev...
    Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho S...
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    TVLSI
    2002
    121views more  TVLSI 2002»
    On-chip decoupling capacitor optimization using architectural level prediction
    13 years 8 months ago
    On-chip decoupling capacitor optimization using architectural level prediction
    Download  users.ece.gatech.edu
    Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
    Mondira Deb Pant, Pankaj Pant, D. Scott Wills
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    ICPPW
    2006
    IEEE
    108views Distributed And Parallel Com...» more  ICPPW 2006»
    Towards a Source Level Compiler: Source Level Modulo Scheduling
    14 years 2 months ago
    Towards a Source Level Compiler: Source Level Modulo Scheduling
    Download  cs.haifa.ac.il
    Modulo scheduling is a major optimization of high performance compilers wherein The body of a loop is replaced by an overlapping of instructions from different iterations. Hence ...
    Yosi Ben-Asher, Danny Meisler
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    ISQED
    2007
    IEEE
    140views Hardware» more  ISQED 2007»
    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
    14 years 3 months ago
    Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
    Download  www.ce.chalmers.se
    We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
    Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
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