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» The High Level Architecture for Simulations
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ENGL
2008
118views more  ENGL 2008»
13 years 8 months ago
Hybrid Architecture of Genetic Algorithm and Simulated Annealing
This paper discusses novel dedicated hardware architecture for hybrid optimization based on Genetic algorithm (GA) and Simulated Annealing (SA). The proposed architecture achieves ...
Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Tera...
SIMUTOOLS
2008
13 years 10 months ago
SIMCAN: a SIMulator framework for computer architectures and storage networks
This paper presents an OMNeT-based Framework to simulate large complex storage networks, with its corresponding underlying subsystems (I/O, Networking, etc.). With this Framework,...
Alberto Nuñez, Javier Fernández, Jos...
DAC
1997
ACM
14 years 28 days ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
14 years 2 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...
ICCD
2006
IEEE
275views Hardware» more  ICCD 2006»
14 years 5 months ago
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
Tinoosh Mohsenin, Bevan M. Baas