202 search results - page 13 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
TVLSI
2010
13 years 2 months ago
2010
Program code in a computer system can be altered either by malicious security attacks or by various faults in microprocessors. At the instruction level, all code modifications are ...
ISCAPDCS
2003
13 years 9 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
The available Instruction Level Parallelism in Java bytecode (Java-ILP) is not readily exploitable using traditional in-order or out-of-order issue mechanisms due to dependencies ...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...