202 search results - page 14 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
MICRO
1991
IEEE
13 years 11 months ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
HPCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
The continuing miniaturization of technology coupled with wireless networks has made it feasible to physically embed sensor network systems into the environment. Sensor net proces...
HPCA
2008
IEEE
14 years 2 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...