202 search results - page 18 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
HICSS
1997
IEEE
14 years 29 days ago
1997
IEEE
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
MICRO
1997
IEEE
14 years 28 days ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...