202 search results - page 25 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
CASES
2005
ACM
13 years 9 months ago
2005
ACM
In Simultaneous Multithreaded (SMT) architectures most hardware resources are shared between threads. This provides a good cost/performance trade-off which renders these architec...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...