202 search results - page 32 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
LCPC
2004
Springer
14 years 27 days ago
2004
Springer
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
CF
2010
ACM
14 years 19 days ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...