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VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 8 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
MICRO
2006
IEEE
89views Hardware» more  MICRO 2006»
14 years 1 months ago
DMDC: Delayed Memory Dependence Checking through Age-Based Filtering
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
Fernando Castro, Luis Piñuel, Daniel Chaver...
ESTIMEDIA
2009
Springer
14 years 2 months ago
Software parallel CAVLC encoder based on stream processing
—Real-time encoding of high-definition H.264 video is a challenge to current embedded programmable processors. Emerging stream processing methods supported by most GPUs and progr...
Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Z...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
13 years 12 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
CASES
2006
ACM
13 years 11 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu