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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 1 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
14 years 1 months ago
Synonymous address compaction for energy reduction in data TLB
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, M...
IPPS
2006
IEEE
14 years 1 months ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
14 years 28 days ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks
SP
2010
IEEE
158views Security Privacy» more  SP 2010»
13 years 11 months ago
Tamper Evident Microprocessors
Abstract—Most security mechanisms proposed to date unquestioningly place trust in microprocessor hardware. This trust, however, is misplaced and dangerous because microprocessors...
Adam Waksman, Simha Sethumadhavan