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» The MOLEN Processor Prototype
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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
14 years 1 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
ASPDAC
2005
ACM
72views Hardware» more  ASPDAC 2005»
13 years 9 months ago
TERPS: the embedded reliable processing system
Abstract — TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TE...
Hongxia Wang, Samuel Rodríguez, Cagdas Diri...
MICRO
2008
IEEE
113views Hardware» more  MICRO 2008»
14 years 2 months ago
From SODA to scotch: The evolution of a wireless baseband processor
With the multitude of existing and upcoming wireless standards, it is becoming increasingly difficult for hardware-only baseband processing solutions to adapt to the rapidly chan...
Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, ...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 1 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...
ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 5 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner