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ISCA
2005
IEEE
131views Hardware» more  ISCA 2005»
14 years 2 months ago
BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging
Significant time is spent by companies trying to reproduce and fix the bugs that occur for released code. To assist developers, we propose the BugNet architecture to continuousl...
Satish Narayanasamy, Gilles Pokam, Brad Calder
HICSS
1997
IEEE
120views Biometrics» more  HICSS 1997»
14 years 1 months ago
Building the 4 Processor SB-PRAM Prototype
The SB-PRAM is a massively parallel, uniform memory access (UMA) shared memory computer. The main ideas of the design are multithreading on instruction level, hashing of the addre...
Peter Bach, Michael Braun, Arno Formella, Jör...
BIOADIT
2006
Springer
14 years 16 days ago
MOVE Processors That Self-replicate and Differentiate
Abstract. This article describes an implementation of a basic multiprocessor system that exhibits replication and differentiation abilities on the POEtic tissue, a programmable har...
Joël Rossier, Yann Thoma, Pierre-André...
JUCS
2007
114views more  JUCS 2007»
13 years 8 months ago
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
Susana Ortega-Cisneros, Juan Jóse Raygoza-P...
ICS
2005
Tsinghua U.
14 years 2 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...