Sciweavers

314 search results - page 57 / 63
» The Nachos Instructional Operating System
Sort
View
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 2 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
ISCA
2003
IEEE
157views Hardware» more  ISCA 2003»
14 years 2 months ago
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
Scaling of CMOS technology causes the power supply voltages to fall and supply currents to rise at the same time as operating speeds are increasing. Falling supply voltages cause ...
Michael D. Powell, T. N. Vijaykumar
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
14 years 1 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
AAAI
1990
13 years 10 months ago
The Design of a Marker Passing Architecture for Knowledge Processing
Knowledge processing is very demanding on computer architectures. Knowledge processing generates subcomputation paths at an exponential rate. It is memory intensive and has high c...
Wing Lee, Dan I. Moldovan
EUROSYS
2009
ACM
14 years 5 months ago
Pointless tainting?: evaluating the practicality of pointer tainting
This paper evaluates pointer tainting, an incarnation of Dynamic Information Flow Tracking (DIFT), which has recently become an important technique in system security. Pointer tai...
Asia Slowinska, Herbert Bos