1542 search results - page 12 / 309 » The Observational Power of Clocks |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
— We propose a sensitivity-based method to allocate decaps incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate d...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...