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» The Power of Hybrid Acceleration
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ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 3 months ago
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates
Abstract— This paper quantifies the impact of threshold voltage variation on aging-related hard failure rates in a highperformance 65nm processor. Simulations show that threshol...
Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
DAC
2005
ACM
13 years 11 months ago
Keeping hot chips cool
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
14 years 1 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba
NOCS
2007
IEEE
14 years 3 months ago
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing
Dynamic routing can substantially enhance the quality of service for multiprocessor communication, and can provide intelligent adaptation of faulty links during run time. Implemen...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
IPPS
2007
IEEE
14 years 3 months ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...