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ASPLOS
2010
ACM
13 years 11 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
SODA
2008
ACM
100views Algorithms» more  SODA 2008»
13 years 9 months ago
A tight lower bound for parity in noisy communication networks
We show a tight lower bound of (N log log N) on the number of transmission required to compute the parity of N bits (with constant error) in a network of N randomly placed sensors...
Chinmoy Dutta, Yashodhan Kanoria, D. Manjunath, Ja...
MJ
2007
119views more  MJ 2007»
13 years 7 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
HPCA
2007
IEEE
14 years 8 months ago
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
Kiran Puttaswamy, Gabriel H. Loh
AFRICACRYPT
2009
Springer
14 years 2 months ago
Breaking KeeLoq in a Flash: On Extracting Keys at Lightning Speed
We present the first simple power analysis (SPA) of software implementations of KeeLoq. Our attack drastically reduces the efforts required for a complete break of remote keyless...
Markus Kasper, Timo Kasper, Amir Moradi, Christof ...