Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
We show a tight lower bound of (N log log N) on the number of transmission required to compute the parity of N bits (with constant error) in a network of N randomly placed sensors...
Chinmoy Dutta, Yashodhan Kanoria, D. Manjunath, Ja...
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
We present the first simple power analysis (SPA) of software implementations of KeeLoq. Our attack drastically reduces the efforts required for a complete break of remote keyless...
Markus Kasper, Timo Kasper, Amir Moradi, Christof ...