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DAC
2007
ACM
16 years 5 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
145
Voted
STOC
1993
ACM
141views Algorithms» more  STOC 1993»
15 years 8 months ago
Bounds for the computational power and learning complexity of analog neural nets
Abstract. It is shown that high-order feedforward neural nets of constant depth with piecewisepolynomial activation functions and arbitrary real weights can be simulated for Boolea...
Wolfgang Maass
TCSV
2008
130views more  TCSV 2008»
15 years 4 months ago
Fast H.264/MPEG-4 AVC Transcoding Using Power-Spectrum Based Rate-Distortion Optimization
Since variable block-size motion compensation (MC) and rate-distortion optimization (RDO) techniques are adopted in H.264/MPEG-4 AVC, modes and motion vectors (MVs) in input stream...
Huifeng Shen, Xiaoyan Sun, Feng Wu
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
16 years 1 months ago
On capture power-aware test data compression for scan-based testing
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, ...
121
Voted
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
15 years 9 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...