Sciweavers

598 search results - page 33 / 120
» The Puzzle Layout Problem
Sort
View
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
WSC
2008
13 years 10 months ago
Representing layout information in the CMSD specification
Developing mechanisms for the efficient exchange of information between simulations and other manufacturing tools is a critical problem. For many areas of manufacturing, neither r...
Frank Riddick, Y. Tina Lee
EOR
2007
93views more  EOR 2007»
13 years 7 months ago
Contour line construction for a new rectangular facility in an existing layout with rectangular departments
In a recent paper, Savas, Batta and Nagi [14] consider the optimal placement of a finite-sized facility in the presence of arbitrarily-shaped barriers under rectilinear travel. T...
Hari Kelachankuttu, Rajan Batta, Rakesh Nagi
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 1 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
ISPD
1998
ACM
128views Hardware» more  ISPD 1998»
13 years 11 months ago
Topology constrained rectilinear block packing for layout reuse
In this paper, we formulate the problem of topology constrained rectilinear block packing in layout reuse. A speci c class of rectilinear shaped blocks, ordered convex rectilinear...
Maggie Zhiwei Kang, Wayne Wei-Ming Dai