6271 search results - page 1220 / 1255 » The RACE network architecture |
VIS
2006
IEEE
2006
IEEE
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
14 years 11 months ago
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
GIS
2007
ACM
14 years 11 months ago
2007
ACM
This paper presents an approach to visualize and analyze 3D building information models within virtual 3D city models. Building information models (BIMs) formalize and represent d...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
DAC
1999
ACM
14 years 11 months ago
1999
ACM
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
DAC
2003
ACM
14 years 11 months ago
2003
ACM
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...