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133
Voted
ICCAD
2002
IEEE
16 years 16 days ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
126
Voted
SOSP
2009
ACM
16 years 16 days ago
2009
ACM
Faulty device drivers cause significant damage through down time and data loss. The problem can be mitigated by an improved driver development process that guarantees correctness...
121
Voted
BIBE
2007
IEEE
15 years 10 months ago
2007
IEEE
— Methods for reliable synthesis of long genes offer great promise for protein synthesis via expression of synthetic genes, with applications to improved analysis of protein stru...
125
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ISQED
2007
IEEE
15 years 10 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
137
Voted
ICCAD
1999
IEEE
15 years 8 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...