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138
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ICCAD
1998
IEEE
120views Hardware» more  ICCAD 1998»
15 years 8 months ago
Communication synthesis for distributed embedded systems
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
Ross B. Ortega, Gaetano Borriello
CODES
2004
IEEE
15 years 7 months ago
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
Hyunuk Jung, Soonhoi Ha
121
Voted
ASPDAC
2008
ACM
169views Hardware» more  ASPDAC 2008»
15 years 5 months ago
Buffered clock tree synthesis for 3D ICs under thermal variations
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
Jacob R. Minz, Xin Zhao, Sung Kyu Lim
105
Voted
TOPNOC
2008
15 years 3 months ago
Assessing State Spaces Using Petri-Net Synthesis and Attribute-Based Visualization
State spaces are commonly used representations of system behavior. A state space may be derived from a model of system behavior but can also be obtained through process mining. For...
H. M. W. (Eric) Verbeek, A. Johannes Pretorius, Wi...
MCSS
2007
Springer
15 years 3 months ago
Minimal symmetric Darlington synthesis
We consider the symmetric Darlington synthesis of a p × p rational symmetric Schur function S with the constraint that the extension is of size 2p×2p. Under the assumption that S...
Laurent Baratchart, P. Enqvist, A. Gombani, M. Oli...