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VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
14 years 12 days ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
14 years 22 days ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
PLDI
2003
ACM
14 years 22 days ago
Taming the IXP network processor
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
Lal George, Matthias Blume
DAC
2004
ACM
14 years 28 days ago
Low voltage swing logic circuits for a Pentium 4 processor integer core
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
Daniel J. Deleganes, Micah Barany, George Geannopo...