Sciweavers

4679 search results - page 4 / 936
» The Timely Computing Base Model and Architecture
Sort
View
ISORC
2005
IEEE
14 years 2 months ago
Model-Checking of Component-Based Event-Driven Real-Time Embedded Software
As complexity of real-time embedded software grows, it is desirable to use formal verification techniques to achieve a high level of assurance. We discuss application of model-ch...
Zonghua Gu, Kang G. Shin
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
PDPTA
2004
13 years 9 months ago
Static Performance Evaluation for Memory-Bound Computing: The MBRAM Model
We present the MBRAM model for static evaluation of the performance of memory-bound programs. The MBRAM model predicts the actual running time of a memory-bound program directly fr...
Gene Cooperman, Xiaoqin Ma, Viet Ha Nguyen
DAC
2003
ACM
14 years 9 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou
ISORC
1998
IEEE
14 years 20 days ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz